Maurizio Palesi and Masoud Daneshtalab. Routing Algorithms in NetworksonChip.
Springer. ISBN 9781461482734.
Journal Papers
A. Mineo, M. Palesi, G. Ascia, V. Catania. Runtime Tunable Transmitting Power Technique in mmWave WiNoC Architectures. Accepted for publication in IEEE Transactions on Very Large Scale Integration Systems, 2015.
N. Jafarzadeh, M. Palesi, S. Eskandari, S. Hessabi, A. AfzaliKusha. Low Energy yet Reliable Data Communication Scheme for Networks on Chip. Accepted for publication in IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 2015.
M. Tang, X. Lin, M. Palesi. Routing Pressure: A ChannelRelated and TrafficAware Metric of Routing Algorithm. IEEE Transactions on Parallel and Distributed Systems. 26(3), Mar. 2015.
M. Palesi, M. Collotta, A. Mineo, V. Catania. An Efficient Radio Access Control Mechanism for Wireless NetworkonChip Architectures. Journal of Low Power Electronics and Applications. 5(2) pp. 3856, 2015.
M. Palesi, D. Patti, G. Ascia, D. Panno, V. Catania. Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. Journal of Computer Science, Science Publications, 11(3), pp. 552566, 2015.
M. Tang, X. Lin, M. Palesi. An Offline Method for Designing Adaptive Routing Based on Pressure Model. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems. 34(2), Feb. 2015, pp. 307320.
X. Wang, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi, T. Mak. On Selftuning NetworksonChip for Dynamic NetworkFlow Dominance Adaptation. ACM Transactions on Embedded Computing Systems. 13(2), Jan. 2014.
N. Jafarzadeh, M. Palesi, A. Khademzadeh, A. AfzaliKusha. Data Encoding Techniques for Reducing Energy Consumption in Networks on Chip. IEEE Transactions on Very Large Scale Integration (VLSI). 22(3), Mar. 2014.
M. Daneshtalab, M. Palesi, J. Plosila, A. Hemani. Editorial of the Special issue on Manycore Embedded Systems. Elsevier Microprocessors and Microsystems, 38(6), Aug. 2014.
X. Wang, M. Yang, Y. Jiang, M. Palesi, P. Liu, T. Mak, N. Bagherzadeh.Efficient multicast schemes for 3D NetworksonChip. Journal of Systems Architecture, 59(9), Oct. 2013, pp. 693–708.
F. Shen, M. Palesi, M. Yang. Guest Editors Introduction to the Special Issue on Novel OnChip Parallel Architectures and Software Support. Parallel Computing Journal, September 2013.
T. Mak, M. Palesi, M. Daneshtalab. Editorial of the Special Issue on Emerging OnChip Networks and Architectures. IET Computers & Digital Techniques, 2013. doi: 10.1049/ietcdt.2013.0144
X. Wang, P. Liu, M. Yang, M. Palesi, Y. Jiang, M. C. Huang. Energy Efficient RunTime Incremental Mapping for 3D NetworksonChip. Springer, Journal of Computer Science and Technology, 28(1), pp. 5471, January 2013.
M. Palesi, R. Tornero, J. M. Orduna, D. Panno, V. Catania. Designing Robust Routing Algorithms and Mapping Cores in NetworksonChip: A Multiobjective Evolutionarybased Approach. Journal of Universal Computer Science. 18(7), pp. 937969.
D. Patti, A. Spadaccini, M. Palesi, F. Fazzino, V. Catania. Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. IEEE Transactions on Education. 55(3), pp. 406411, Aug 2012.
R. AlDujaily, T. Mak, F. Xia, A. Yakovlev, M. Palesi. Embedded Transitive Closure Network for RunTime Deadlock Detection in NetworksonChip. IEEE Transactions on Parallel and Distributed Systems, 23(7), pp. 12051215, July 2012.
F. Shen, M. Yang, M. Palesi: Guest Editors' Introduction to the Special Issue on Emerging Computing Architectures and Systems. Computers & Electrical Engineering 38(3): 722723, 2012.
M. Palesi, S. Kumar, R. Marculescu. Editorial of the Special Issue on Network on Chip Architectures and Design Methodologies. Elsevier Microprocessors and Microsystems Journal. Jan 2011.
M. Palesi, G. Ascia, F. Fazzino, V. Catania. Data Encoding Schemes in Networks on Chip. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 30(5), May 2011.
M. Yang, Y. Jiang, P. Liu, M. Palesi. Editorial of the Special Issue on PowerEfficient, High Performance General Purpose and Application Specific Computing Architectures. International Journal of High Performance Systems Architecture. 2(3/4), 2010.
G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, D. Patti. Performance Evaluation of Efficient MultiObjective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems. Applied Soft Computing, 11(1), pp. 382398, January 2011.
M. Palesi, S. Kumar, V. Catania. Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 29(3), pp. 426440, March 2010.
M. Palesi, S. Kumar, V. Catania. Bandwidth Aware Routing Algorithms for NetworksonChip Platforms. Computers & Digital Techniques, IET, Vol. 3, No. 5. (11 August 2009), pp. 413429.
M. Palesi, R. Holsmark, S. Kumar, V. Catania. Application Specific Routing Algorithms for Networks on Chip. IEEE Transactions on Parallel and Distributed Systems, 20(3), pp. 316330, March 2009.
A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark and J. Duato.RegionBased Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs IEEE Transactions on on Very Large Scale Integration Systems, 17(3), pp. 356369, March 2009.
G. Ascia, V. Catania, M. Palesi, D. Patti. Implementation and Analysis of a New Selection Strategy for Adaptive Routing in NetworksonChip. IEEE Transactions on Computers, 57(6), pp. 809820, June 2008.
V. Catania, M. Palesi, D. Patti. Reducing Complexity of Multiobjective Design Space Exploration in VLIWbased Embedded Systems. ACM Transactions on Architecture and Code Optimization, 5(2), pp.11:111:33, Aug. 2008.
V. Catania, M. Palesi, D. Patti. Analysis and Tools for the Design of VLIW Embedded Systems in a Multiobjective Scenario. Journal of Circuits Systems and Computers, 16(5), pp. 819846, Oct. 2007.
R. Holsmark, M. Palesi, S. Kumar. Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions. Journal of Systems Architecture, 54/34 (2008) pp. 427440.
D. Bertozzi, S. Kumar, M. Palesi. NetworksonChip: Emerging Research Topics and Novel Ideas. VLSI Design, vol. 2007, Article ID 26454, doi:10.1155/2007/26454.
G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. Efficient Design Space Exploration for Application Specific SystemsonaChip. Journal of Systems Architecture, 53(10), pp. 733750, Oct. 2007.
G. Ascia, V. Catania, M. Palesi. A Multiobjective Genetic Approach to Mapping Problem on NetworkonChip. Journal of Universal Computer Science, 12(4):370394, 2006.
G. Ascia, V. Catania, M. Palesi. Mapping Cores on NetworkonChip. International Journal of Computational Intelligence Research (IJCIR), ISSN 09729836 , 1(12):109126, 2005.
G. Ascia, V. Catania, M. Palesi, and A. Parlato. Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach. IEE Proceeding on Computers & Digital Techniques, 152(6):756764, November 2005.
G. Ascia, V. Catania, and M. Palesi. A Multiobjective Genetic Approach for Systemlevel Exploration in Parameterized Systemsonachip. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 24(4):635645, April 2005.
G. Ascia, V. Catania, and M. Palesi. A GA Based Design Space Exploration Framework for Parameterized SystemonaChip Platforms. IEEE Transactions on Evolutionary Computation, 8(2):329346, August 2004.
G. Ascia, V. Catania, M. Palesi, and D.Sarta. An instructionlevel power analysis model with data dependency. VLSI Design, 12(2):245273, 2001.
Chapter in Books
M. Daneshtalab, M. Palesi. Basic Concepts on OnChip Networks. In Routing Algorithms in NetworksonChip. Springer. 2013
R. AlDujaily, T. Mak, F. Xia, A. Yakovlev, and M. Palesi. RunTime Deadlock Detection. In Routing Algorithms in NetworksonChip. Springer. 2013
M. Palesi, R. Holsmark, S. Kumar, and V. Catania. Application Specific Routing Algorithms for Low Power Network on Chip Design. Low Power NetworksonChip, Springer.
G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, and D. Patti. Computational Intelligence to SpeedUp MultiObjective Design Space Exploration of Embedded Systems. MultiObjective Optimization in Computational Intelligence: Theory and Practice. Lam Thu Bui (editor), Sameer Alam (editor), Chapter X, pp. 265299, 2008.
G. Ascia, V. Catania, and M. Palesi. An evolutionary approach for Paretooptimal configurations in SOC platforms. In Kluwer Academic Pulishers, editor, SOC Design Methodologies, 2002.
G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In Kluwer Academic Pulishers, editor, System on Chip for Realtime Systems, 2002.
Conference Papers
V. Catania, A. Mineo, S. Monteleone, M. Palesi, D. Patti. Noxim: An Open, Extensible and Cycleaccurate Network on Chip Simulator. Accepted for IEEE International Conference on Applicationspecific Systems, Architectures and Processors 2015 takes place July 2729, 2015 in Toronto, Canada.
A. Mineo, M. S. Rusli, M. Palesi, G. Ascia, V. Catania, and M. N. Marsono. A Closed Loop Transmitting Power SelfCalibration Scheme for Energy Efficient WiNoC Architectures. Design Automation and Test in Europe (DATE 2015). Grenoble, France, March 912, 2015.
M. Fattah, M. Palesi, P. Liljeberg, H. Tenhunen. SHiFA: SystemLevel Hierarchy in RunTime FaultAware Management of ManyCore Systems. Design Automation Conference (DAC 2014). DAC 2014. June 15, 2014.
A. Mineo, M. Palesi, G. Ascia, V. Catania. An Adaptive Transmitting Power Technique for Energy Efficient mmWave Wireless NoCs. Design Automation and Test in Europe (DATE 2014). Dresden, Germany, March 2428, 2014.
X. Wang, B. Zhao, T. Mak, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi. Adaptive Power Allocation for Manycore Systems Inspired from A Multiagent Auction Model. Design Automation and Test in Europe (DATE 2014). Dresden, Germany, March 2428, 2014.
M. Masi, A. Mineo, M. Palesi, G. Ascia, V. Catania. Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. 11th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2013), Zhangjiajie, China, November 1315, 2013.
A. Mineo, M. Palesi, G. Ascia, V. Catania. Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. EUROMICRO DSD/SEAA 2013, Santander, Spain, September 46, 2013.
G. Ascia, M. Palesi, V. Catania. An adaptive output selection function based on a fuzzy rule base system for Network on Chip. EUROMICRO DSD/SEAA 2013, Santander, Spain, September 46, 2013.
A. Mineo, M. Palesi, G. Ascia, V. Catania. NoC Links Energy Reduction through Link Voltage Scaling. 13th International Conference on Embedded Computer Systems: Architectures, Modeling, and Siimulation (SAMOS XIII), Samos, Greece, July 15–18, 2013.
X. Wang, T. Mak, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi. On SelfTuning NetworksonChip for Dynamic NetworkFlow Dominance Adaptation. To be presented at 7th ACM/IEEE International Symposium on NetworksonChip (NOCS), April 2013, Tempe, Arizona.
M. Ebrahimi, M. Daneshtalab, F. Farahnakian, P. Liljeberg, J. Plosila, M. Palesi, and H. Tenhunen, "HARAQ: CongestionAware Learning Model for Highly Adaptive Routing Algorithm in OnChip Networks," in Proceedings of 6th ACM/IEEE International Symposium on NetworksonChip (NOCS), pp. 1926, May. 2012, Denmark.
D. Patti, A. Spadaccini, M. Palesi, F. Fazzino, and V. Catania. Improving the Teaching Effectiveness in an Introductory Computer Architecture Course. International Conference on Computational Intelligence and Software Engineering, 2011.
X. Wang, M. Palesi, M. Yang, Y. Jiang, M. C. Huang, P. Liu. PowerAware RunTime Incremental Mapping for 3D NetworksonChip. Lecture Notes in Computer Science, vol. 6985, Network and Parallel Computing Conference, 2011.
X. Wang, M. Palesi, M. Yang, Y. Jiang, M. C. Huang, P. Liu. Low Latency and Energy Efficient Multicasting Schemes for 3D NoCbased SoCs. VLSI System on Chip. October 2011, Kowloon, Hong Kong, China.
D. Salemi, M. Palesi, V. Catania. PowerAware Selection Policy for Networks on Chip. 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS'11). 68 APril 2011, Athens, Greece.
AlDujaily, T. Mak, F. Xia, A. Yakovlev, M. Palesi. Runtime Deadlock Detection in NetworksonChip using Coupled Transitive Closure Networks. Design Automation and Test in Europe (DATE 2011). 1418 March 2011, Grenoble, France. Best Paper Award
R. Holsmark, S. Kumar, M. Palesi. A MultiLevel Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms. 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010), August 31, 2010, Ischia Naples, Italy. [To appear]
M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. A Novel Mechanism to Guarantee InOrder Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. 13th Euromicro Conference On Digital System Design Architectures, Methods and Tools Lille, France, 13 September, 2010. [To appear]
M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. An Adaptive Routing Technique Supporting InOrder Packet Delivery in Networks on Chip. 4th Workshop on Interconnection Network Architectures: OnChip, MultiChip, held in conjunction with the: 5th International Conference on High Performance Embedded Architectures and Compilers, Pisa, Italy, January 24, 2010.
M. Palesi and S. Kumar. Message from the Chairs. 2nd International Workshop on Network on Chip Architectures, held in conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Dec 12, 2009, New York, New York, USA.
G. Ascia, V. Catania, F. Fazzino, M. Palesi. An Encoding Scheme to Reduce Power Consumption in NetworksonChip. IEEE International Conference on Computer Engineering and Systems, 1416 Dec 2009, Cairo, Egypt.
V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti. An Effective Methodology to Multiobjective Design of Application Domainspecific Embedded architectures. 12th Euromicro Conference on Digital System Design, 2729 Aug 2009, Patras, Greece.
M. Palesi, F. Fazzino, G. Ascia, V. Catania. Data Encoding for LowPower in WormholeSwitched NetworksonChip. 12th Euromicro Conference on Digital System Design, 2729 Aug 2009, Patras, Greece.
R. Tornero, V. Sterrantino, M. Palesi, J. M. Orduna. A Multiobjective Strategy for Concurrent Mapping and Routing in Networks on Chip. IEEE/ACM International Symposium on Parallel & Distributed Processing, 2528 May, 2009, Rome, Italy.
R. Holsmark, M. Palesi, S. Kumar, A. Mejia. HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip. 3rd ACM/IEEE International Symposium on Networks on Chip. May 1013, 2009, San Diego, CA
D. Frazzetta, G. Dimartino, M. Palesi, S. Kumar, V. Catania. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 1825, Sep. 35, 2008, Parma, Italy.
V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti. High Performance Computing for Embedded System Design: A Case Study. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 656659, Sep. 35, 2008, Parma, Italy.
R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A CommunicationAware Topological Mapping Technique for NoCs. International Conference on Parallel and Distributed Computing, pp. 910919, August 2629th, 2008, Las Palmas de Gran Canaria, Spain.
M. Palesi, G. Longo, S. Signorino, S. Kumar, R. Holsmark, V. Catania. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for NetworksonChip Platforms. IEEE International Symposium on NetworksonChip, pp. 97106, 7th11th April 2008, Newcastle University, UK.
G. Longo, S. Signorino, M. Palesi, S. Kumar, R. Holsmark, V. Catania.Bandwidth Aware Routing Algorithms for NetworksonChip. 2nd Workshop on Interconnection Network Architectures: OnChip, MultiChip. Goteborg, Sweden, January 27, 2008.
R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A CommunicationAware Task Mapping Technique for NoCs. 2nd Workshop on Interconnection Network Architectures: OnChip, MultiChip. Goteborg, Sweden, January 27, 2008.
M. Palesi, S. Kumar, R. Holsmark, V. Catania. Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IEEE International Parallel and Distributed Processing Symposium, pp. 18, Long Beach, CA, March 2007.
A. G. Di Nuovo, M. Palesi, V. Catania. MultiObjective Evolutionary Fuzzy Clustering for HighDimensional Problems. IEEE International Fuzzy Systems Conference. pp. 16, July 2007.
G. Ascia, V. Catania, M. Palesi, D. Patti. NeighborsonPath: A New Selection Strategy for OnChip Networks. Fourth IEEE Workshop on Embedded Systems for Real Time Multimedia, pp. 7984. Seoul, Korea, October 2627, 2006.
M. Palesi, R. Holsmark, S. Kumar, V. Catania. A Methodology for Design of Application Specific Deadlockfree Routing Algorithms for NoC Systems. International Conference on HardwareSoftware Codesign and System Synthesis, pp. 142147. Seoul, Korea, October 2225, 2006.
G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. Fuzzy Decision Making in Embedded System Design. International Conference on HardwareSoftware Codesign and System Synthesis, Seoul, Korea, October 2225, 2006.
R. Holsmark, M. Palesi, S. Kumar. Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006, 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 696703. Croatia, Sept 2006.
M. Palesi, S. Kumar, R. Holsmark. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 373384. Samos, Greece, July 1720, 2006.
G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. An Efficient Hierarchical Fuzzy Approach for System Level SystemonaChip Design. ICSAMOS: Embedded
Computer Systems: Architectures, Modeling, and Simulation. Samos, Greece, July 1720, 2006.
G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. A Multiobjective Genetic Fuzzy Approach for Intelligent Systemlevel Exploration in Parameterized VLIW Processor Design. IEEE Congress on Evolutionary Computation to be held in Sheraton Vancouver Wall Centre, Vancouver, BC, Canada, July 2006.
G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti.Fuzzy Simulation to Speedup Computer Design. In 4th Industrial Simulation Conference, pp. 285289, Palermo, Italy, June 57 2006.
G. Ascia, V. Catania, M. Palesi, D. Patti. A New Selection Policy for Adaptive Routing in Network on Chip. International Conference on Electronics, Hardware, Wireless and Optical Communications. Madrid, Spain, February 1517, 2006.
G. Ascia, V. Catania, M. Palesi. An Evolutionary Approach to NetworkonChip Mapping Problem. IEEE Congress on Evolutionary Computation. Edinburgh, UK, September 2nd5th, 2005.
G. Ascia, V. Catania, M. Palesi, D. Patti. Exploring Design Space of VLIW Architectures. IEEE 16th International Conference on Applicationspecific Systems, Architectures and Processors. Samos, Greece, July 2325, 2005.
G. Ascia, V. Catania, M. Palesi, D. Patti. Hyperblock Formation: A Power/Energy Perspective for High Performance VLIW Architectures. IEEE International Symposium on Circuits and Systems 2005, Japan, May 2126, 2005.
G. Ascia, V. Catania, M. Palesi, D. Patti. A Systemlevel Framework for Evaluating Area/Performance/Power Tradeoffs of VLIWbased Embedded Systems. Asia and South Pacific Design Automation Conference 2005, Shanghai, Cina, Jan. 1821, 2005.
G. Ascia, V. Catania, M. Palesi, D. Patti. Power/Energy Perspective on Hyperblock Formation. International Conference on High Performance Computing. Bangalore, India, December 1922, 2005.
G. Ascia, V. Catania, M. Palesi. Multiobjective Mapping for Meshbased NoC Architectures. In Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pages 182187, Stockholm, Sweden, Sept. 810, 2004.
G. Ascia, V. Catania, M. Palesi, and D. Patti. MultiObjective Optimization of a Parameterized VLIW Architecture. In NASA/DoD Conference on Evolvable Hardware, Seattle, Washington, USA, Jun.2426 2004.
G. Ascia, V. Catania, M. Palesi, and A. Parlato. An evolutionary approach for reducing the switching activity in address buses. In Congress on Evolutionary Computation, Canberra, Australia, Dec.812 2003.
G. Ascia, V. Catania, M. Palesi, and A. Parlato. A genetic approach to bus encoding. In IFIP International Conference on Very Large Scale Integration, Dec. 13 2003.
G. Ascia, V. Catania, M. Palesi, and D. Patti. EPICExplorer: A parameterized VLIWbased platform framework for design space exploration. In First Workshop on Embedded Systems for RealTime Multimedia (ESTIMedia), Newport Beach, California, USA, Oct. 34 2003.
G. Ascia, V. Catania, M. Palesi, and A. Parlato. An evolutionary approach for reducing the energy in address buses. In International Symposium on Information and Communication Technologies, Sept. 2426 2003.
G. Ascia, V. Catania, and M. Palesi. A genetic bus encoding technique for power optimization of embedded systems. In 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, Italy, Sept. 1012 2003.
G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In International Workshop on SystemonChip for RealTime Applications, Banff, Canada, July 67 2002.
G. Ascia, V. Catania, and M. Palesi. Design space exploration methodologies for IPbased systemonachip. In IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, May 2629 2002.
M. Palesi and T.Givargis. Multiobjective design space exploration using genetic algorithms. In Tenth International Symposium on Hardware/Software Codesign, Stanley Hotel, Estes Park, Colorado, USA, May 68 2002.
G. Ascia, V. Catania, and M. Palesi. A framework for design space exploration of parameterized VLSI systems. In 7th Asia and South Pacific Design Automation Conference & 15th International Conference on VLSI Design, Bangalore, India, Jan. 711 2002.
G. Ascia, V. Catania, and M. Palesi. A novel approach to design space exploration of parameterized SOCs. In IFIP International Conference on Very Large Scale Integration, The Global System on Chip Design & CAD Conference, 11th edition, pages 449454, Montpellier, France, Dec. 25 2001.
G. Ascia, V. Catania, and M. Palesi. Parameterized system design based on genetic algorithms. In 9th. International Symposium on Hardware/Software CoDesign, pages 177182, Copenhagen, Denmark, Apr. 2527 2001.
Maurizio Palesi
Associate Professor
: +39 339 180 2626
DEPARTMENTFaculty of Engineering
UKE - Kore University of Enna